cpovex · folio · vol. i

I. Prologue · 2026 —

Allen Huang.

A quiet research surface at the intersection of radio-frequency integrated circuits, co-packaged photonics, and the machine-learning methods that are quietly rewriting how hardware is drawn.

Position PhD Candidate Electrical & Computer Engineering
Station Irvine, CA 33°38′N · 117°50′W
Carrier λ = 1550 nm optical C-band

§ I   Currently

A rolling set of threads occupying the bench this season.

  1. 01

    EDA automation for analog & RF layout

    Scripting Cadence Virtuoso / SKILL into a reproducible pipeline; turning the artisan craft of IC layout into something versioned, testable, and shareable.

  2. 02

    ML-guided placement & routing

    Training models on the geometry of good hand-drawn layouts to propose draft topologies for passives, matching networks, and mmWave routing.

  3. 03

    mmWave PLL / VCO circuit work

    Phase-noise-aware VCO design; injection-locked dividers; wideband phase-locked loops for the next generation of instrumentation and links.

  4. 04

    Co-packaged optics, from the RF side

    Notes on what changes for an RF designer when the signal leaves the die as light instead of as a transmission-line mode. Where the “vex” in cpovex comes from.

§ II   Threads

Long-form writing — currently typesetting.

Essay · forthcoming

Why RF engineers should be watching CPO

A primer for people who draw transmission lines for a living, on the electromagnetic story underneath co-packaged optics.

Notebook · forthcoming

An EDA workflow I wish I had started with

Git-backed Cadence libraries, scripted DRC, and the small daily automations that make analog design feel less like stone-carving.

Field note · forthcoming

Measuring a VCO at 3 a.m.

On patience, on cables, on the particular solitude of a phase-noise sweep that will not converge.

§ III   Reach

The usual channels. Prefers the slow ones.